A Graph Neural Network Framework for Structural Side-Channel Vulnerability Assessment in Cryptographic Circuits
DOI:
https://doi.org/10.66279/0e5j0983Keywords:
Graph neural networks, Circuit topology, Hardware security, Side-channel analysisAbstract
Traditional side-channel analysis treats power and electromagnetic traces as temporal sequences, applying statistical or sequence-based machine learning methods without regard for the circuit topology responsible for generating observed leakage. This discards structural information intrinsic to digital circuits: gate connectivity, signal propagation topology, and the hierarchical organization of cryptographic modules. A framework is presented that applies Graph Neural Networks (GNNs) to side-channel vulnerability assessment by modeling circuits as attributed graphs in which nodes represent logic gates, edges represent wire connections, and power measurements are encoded as node features. A complete pipeline is developed spanning Verilog netlist parsing, graph construction, and Graph Convolutional Network (GCN) training with multi-head attention for multi-scale circuit analysis. Evaluation on ten AES-128 circuit implementations demonstrates an 86.4% attack success rate, compared with 68.1% for a CNN-LSTM baseline, with required power traces reduced from 988 to 790. Cross-architecture generalization reaches 63.5% accuracy on unseen circuit families, substantially above the 18.7% random baseline. Interpretable vulnerability heatmaps localize leakage sources at the gate level, enabling pre-silicon security assessment before fabrication.
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References
[1] P. Kocher, J. Jaffe, and B. Jun, “Differential power analysis,” in Annual international cryptology conference,
pp. 388–397, Springer, 1999.
[2] E. Brier, C. Clavier, and F. Olivier, “Correlation power analysis with a leakage model,” in International workshop on cryptographic hardware and embedded systems, pp. 16–29, Springer, 2004.
[3] H. Maghrebi, T. Portigliatti, and E. Prouff, “Breaking cryptographic implementations using deep learning techniques,” in International Conference on Security, Privacy, and Applied Cryptography Engineering,
pp. 3–26, Springer, 2016.
[4] J. Kim, S. Picek, A. Heuser, S. Bhasin, and A. Hanjalic, “Make some noise. unleashing the power of convolutional neural networks for profiled side-channel analysis,” IACR transactions on cryptographic hardware and embedded systems, pp. 148–179, 2019.
[5] L. Wouters, V. Arribas, B. Gierlichs, and B. Preneel, “Revisiting a methodology for efficient CNN architectures in profiling attacks,” IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 147–168, 2020.
[6] G. Zaid, L. Bossuet, A. Habrard, and A. Venelli, “Methodology for efficient cnn architectures in profiling
attacks,” IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2020, no. 1, pp. 1–36, 2020.
[7] D. K. Duvenaud, D. Maclaurin, J. Iparraguirre, R. Bombarell, T. Hirzel, A. Aspuru-Guzik, and R. P. Adams,
“Convolutional networks on graphs for learning molecular fingerprints,” Advances in neural information processing systems, vol. 28, 2015.
[8] J. Gilmer, S. S. Schoenholz, P. F. Riley, O. Vinyals, and G. E. Dahl, “Neural message passing for quantum chemistry,” in International conference on machine learning, pp. 1263–1272, Pmlr, 2017.
[9] W. Hamilton, Z. Ying, and J. Leskovec, “Inductive representation learning on large graphs,” Advances in neural information processing systems, vol. 30, 2017.
[10] M. Allamanis, M. Brockschmidt, and M. Khademi, “Learning to represent programs with graphs,” arXiv preprint arXiv:1711.00740, 2017.
[11] M. Li, S. Khan, Z. Shi, N. Wang, H. Yu, and Q. Xu, “Deepgate: Learning neural representations of logic gates,” in Proceedings of the 59th ACM/IEEE Design Automation Conference, pp. 667–672, 2022.
[12] Z. Shi, H. Pan, S. Khan, M. Li, Y. Liu, J. Huang, H.-L. Zhen, M. Yuan, Z. Chu, and Q. Xu, “Deepgate2: Functionality-aware circuit representation learning,” in 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1–9, IEEE, 2023.
[13] Z. Dong, W. Cao, M. Zhang, D. Tao, Y. Chen, and X. Zhang, “Cktgnn: Circuit graph neural network for electronic design automation,” arXiv preprint arXiv:2308.16406, 2023.
[14] Y. Fouad, A. N. Ghareeb, E. Selem, et al., “Evolution of routing protocols in wireless sensor networks considering challenges advances and drone-assisted innovations,” Computational Discovery and Intelligent Systems (CDIS), vol. 2, no. 2, pp. 22–41, 2026.
[15] A. Hammad, A. Saad, A. Ibrahim, A. A. Elngar, et al., “Comprehensive analysis of security challenges and mitigation strategies in 5g mobile wireless networks,” Computational Discovery and Intelligent Systems (CDIS), vol. 1, no. 2, pp. 36–42, 2025.
[16] L. Alrahis, S. Patnaik, M. Shafique, and O. Sinanoglu, “Embracing graph neural networks for hardware security,” in Proceedings of the 41st IEEE/ACM international conference on computer-aided design, pp. 1–9, 2022.
[17] Z. El Sayed, Z. Wang, H. Selmani, J. Knechtel, O. Sinanoglu, and L. Alrahis, “Graph neural networks for integrated circuit design, reliability, and security: Survey and tool,” ACM Computing Surveys, vol. 58, no. 4, pp. 1–44, 2025.
[18] T. N. Kipf and M. Welling, “Semi-supervised classification with graph convolutional networks,” arXiv preprint arXiv:1609.02907, 2016.
[19] P. Veličković, G. Cucurull, A. Casanova, A. Romero, P. Lio, Y. Bengio, et al., “Graph attention networks,” in International conference on learning representations, vol. 6, p. 2, Ithaca, 2018.
[20] P. C. Kocher, “Timing attacks on implementations of diffie-hellman, rsa, dss, and other systems,” in Advances in Cryptology—CRYPTO’96: 16th Annual International Cryptology Conference Santa Barbara, California, USA August 18–22, 1996 Proceedings, vol. 1109, pp. 104–113, Springer, 1996.
[21] S. Chari, C. S. Jutla, J. R. Rao, and P. Rohatgi, “Towards sound approaches to counteract power-analysis attacks,” in Annual International Cryptology Conference, pp. 398–412, Springer, 1999.
[22] O. Choudary and M. Kuhn, “Efficient template attacks international conference on smart card research and advanced applications,” 2013.
[23] A. Heuser and M. Zohner, “Intelligent machine homicide: Breaking cryptographic devices using support vector machines,” in International Workshop on Constructive Side-Channel Analysis and Secure Design, pp. 249–264, Springer, 2012.
[24] L. Lerman, G. Bontempi, and O. Markowitch, “A machine learning approach against a masked aes: Reaching the limit of side-channel attacks with a learning model,” Journal of Cryptographic Engineering, vol. 5, no. 2, pp. 123–139, 2015.
[25] S. Picek, A. Heuser, A. Jovic, S. A. Ludwig, S. Guilley, D. Jakobovic, and N. Mentens, “Side-channel analysis and machine learning: A practical perspective,” in 2017 International Joint Conference on Neural Networks (IJCNN), pp. 4095–4102, IEEE, 2017.
[26] G. Perin, L. Wu, and S. Picek, “Exploring feature selection scenarios for deep learning-based side-channel analysis,” IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 828–861, 2022.
[27] S. Hajra, S. Chowdhury, and D. Mukhopadhyay, “Estranet: An efficient shift-invariant transformer network for side-channel analysis,” IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2024, no. 1, pp. 336–374, 2024.
[28] F. Bache, C. Plump, J. Wloka, T. Güneysu, and R. Drechsler, “Evaluation of (power) side-channels in cryptographic implementations,” it Information Technology, vol. 61, no. 1, pp. 15–28, 2019.
[29] O. Bronchain and G. Cassiers, “Bitslicing arithmetic/boolean masking conversions for fun and profit: with application to lattice-based KEMs,” IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 553–588, 2022.
[30] S. Picek, G. Perin, L. Mariot, L. Wu, and L. Batina, “Sok: Deep learning-based physical side-channel analysis,” ACM Computing Surveys, vol. 55, no. 11, pp. 1–35, 2023.
[31] L. Wu, L. Weissbart, M. Krček, H. Li, G. Perin, L. Batina, and S. Picek, “On the attack evaluation and the
generalization ability in profiling side-channel analysis,” Cryptology ePrint Archive, 2020.
[32] K. Xu, W. Hu, J. Leskovec, and S. Jegelka, “How powerful are graph neural networks?,” arXiv preprint arXiv:1810.00826, 2018.
[33] L. Rampášek, M. Galkin, V. P. Dwivedi, A. T. Luu, G. Wolf, and D. Beaini, “Recipe for a general, powerful, scalable graph transformer,” Advances in Neural Information Processing Systems, vol. 35, pp. 14501–14515, 2022.
[34] K. Tiri and I. Verbauwhede, “A logic level design methodology for a secure DPA resistant asic or FPGA implementation,” in Proceedings Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 246–251, IEEE, 2004.
[35] T. Moos, F. Wegener, and A. Moradi, “Dl-la: Deep learning leakage assessment: A modern roadmap for sca evaluations,” IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 552–598,
2021.
[36] G. Cassiers and F.-X. Standaert, “Towards globally optimized masking: From low randomness to low noise rate: Or probe isolating multiplications with reduced randomness and security against horizontal attacks,” IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 162–198, 2019.
[37] S. Mangard, E. Oswald, and T. Popp, Power analysis attacks: Revealing the secrets of smart cards. Springer, 2007.
[38] F. -X. Standaert, T. G. Malkin, and M. Yung, “A unified framework for the analysis of side-channel key recovery attacks,” in Annual international conference on the theory and applications of cryptographic techniques, pp. 443–461, Springer, 2009.
[39] D. P. Kingma and J. Ba, “Adam: A method for stochastic optimization,” arXiv preprint arXiv:1412.6980, 2014.
[40] I. Loshchilov and F. Hutter, “Sgdr: Stochastic gradient descent with warm restarts,” arXiv preprint arXiv:1608.03983, 2016.
[41] kokke, “tiny-AES-c: Small portable AES128/192/256 in C.” https://github.com/kokke/ tiny-AES-c, 2019. Accessed April 2026.
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Data Availability Statement
AES-128 implementations were collected from OpenCores, TinyAES, and custom designs.
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